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Product Brief
AGR18125E 125 W, 1.805 GHz--1.880 GHz, LDMOS RF Power Transistor
Introduction
The AGR18125E is a 125 W, 26 V, N-channel goldmetallized, laterally diffused metal oxide semiconductor (LDMOS) RF power field effect transistor (FET) suitable for global system for mobile communication (GSM), enhanced data for global evolution (EDGE), and multicarrier class AB power amplifier applications. This device is manufactured using advanced LDMOS technology offering state-of-theart performance and reliability. It is packaged in an industry-standard package and is capable of delivering a minimum output power of 125 W which makes it ideally suited for today's RF power amplifier applications.
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Table 1. Thermal Characteristics Parameter Thermal Resistance, Junction to Case: AGR18125EU AGR18125EF Sym Ri JC Ri JC Value 0.5 0.5 Unit C/W C/W
Table 2. Absolute Maximum Ratings* Parameter Drain-source Voltage Gate-source Voltage Total Dissipation at TC = 25 C: AGR18125EU AGR18125EF Derate Above 25 C: AGR18125EU AGR18125EF Operating Junction Temperature Storage Temperature Range Sym Value Unit VDSS 65 Vdc VGS -0.5, 15 Vdc PD PD -- -- TJ 350 350 2.0 2.0 200 W W W/C W/C C C
5B 03 STYLE 1
AGR18125EU (unflanged)
AGR18125EF (flanged)
TSTG -65, 150
Figure 1. Available Packages
Features
Typical performance ratings for GSM EDGE (f = 1.840 GHz, POUT = 50 W) -- Modulation spectrum: @ 400 kHz = -60 dBc. @ 600 kHz = -72 dBc. Typical performance over entire digital communication system (DCS) band: -- P1dB: 125 W typical (typ). -- Power gain: @ P1dB = 13.5 dB. -- Efficiency: @ P1dB = 50% typ. -- Return loss: -10 dB. High-reliability, gold-metallization process. Low hot carrier injection (HCI) induced bias drift over 20 years. Internally matched. High gain, efficiency, and linearity. Integrated ESD protection. 125 W minimum output power. Device can withstand 10:1 voltage standing wave ratio (VSWR) at 28 Vdc, 1.840 GHz, 125 W continuous wave (CW) output power. Large signal impedance parameters available.
* Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
Table 3. ESD Rating* AGR18125E HBM MM CDM Minimum (V) 500 50 1500 Class 1B A 4
* Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. PEAK Devices Agere employs a human-body model (HBM), a machine model (MM), and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114B (HBM), JESD22-A115A (MM), and JESD22-C101A (CDM) standards. Caution: MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be observed.
Agere Systems - Proprietary
AGR18125E 125 W, 1.805 GHz--1.880 GHz, LDMOS RF Power Transistor
Product Brief
Electrical Characteristics
Recommended operating conditions apply unless otherwise specified: TC = 30 C. Table 4. dc Characteristics Parameter Off Characteristics 200 Drain-source Breakdown Voltage (VGS = 0, ID = 400 A) Zero Gate Voltage Drain Leakage Current (VDS = 26 V, VGS = 0 V) On Characteristics Gate Threshold Voltage (VDS = 10 V, ID = 400 A) Drain-source On-voltage (VGS = 10 V, ID = 1 A) Table 5. RF Characteristics Parameter Drain-to-gate Capacitance (VDS = 26 V, VGS = 0 V, f = 1 MHz) Symbol Dynamic Characteristics CRSS COSS -- -- 3.0 48 -- -- pF pF Min Typ Max Unit Forward Transconductance (VDS = 10 V, ID = 1 A) VGS(TH) VDS(ON) VGS(Q) GFS -- -- -- -- -- 9 4.8 -- -- -- Vdc S Gate-source Leakage Current (VGS = 5 V, VDS = 0 V) Symbol V(BR)DSS IGSS IDSS Min 65 -- -- Typ -- Max -- Unit Vdc
-- --
4 200 12
Adc
Adc
Gate Quiescent Voltage (VDS = 26 V, ID = 1200 mA)
0.08
3.8
Vdc
Vdc
Drain-to-source Capacitance (VDS = 26 V, VGS = 0 V, f = 1 MHz) Power Gain (VDS = 26 V, POUT = 125 W, IDQ = 1200 mA)
Functional Tests* (in Supplied Test Fixture) Agere Systems Supplied Test Fixture) GL -- -- 13.5 50 -- -- dB %
Drain Efficiency (VDS = 26 V, POUT = 125 W, IDQ = 1200 mA)
EDGE Linearity Characterization (POUT = 50 W, f = 1.840 GHz, VDS = 26 V, IDQ = 1200 mA) Modulation spectrum @ 400 kHz Modulation spectrum @ 600 kHz
-- P1dB VSWRI -- -- --
-60 -72 125 --
-- -- --
dBc dBc W
Output Power (VDS = 26 V, 1 dB gain compression, IDQ = 1200 mA) Ruggedness (VDS = 26 V, POUT = 30 W, IDQ = 1200 mA, VSWR = 10:1 [all angles])
* Across full DCS band, 1.805 GHz--1.880 GHz.
Input VSWR
No degradation in output power.
2:1
Product Brief
AGR18125E 125 W, 1.805 GHz--1.880 GHz, LDMOS RF Power Transistor
Test Circuit Illustrations for AGR18125E
+ C19 C20 C21 VGG C26 R3 + C14 + R2 C13 C12 C11 C10 C9 C8 Z13 R1 FB1 Z24 C22 C23 C24 C25 VDD
Z21 Z20 Z19
Z22 C17
C18
Z23 RF OUTPUT
Z1 RF INPUT C28
Z2
Z4 C27
Z5
C1
Z6
Z7
Z8
Z9
Z10
Z18
Z17
Z16
Z3 R4
C2
C3 Z14 DUT Z15
C16 1 3
C15
Z11
Z12
2 C5
C4
PINS: 1. DRAIN 2. GATE 3. SOURCE
A. Schematic
Parts List: Murata (R) chip capacitor: C12, C24: 0.01 F GRM40X7R103K100AL. 0603 chip capacitor: C10, C22: 220 pF. Sprague(R) tantalum chip capacitor: C14, C15, C26: 22 F, 35 V. Kreger (R) ferrite bead: FB1 2743D19447. Kemet (R) chip capacitor: C13, C25 0.10 F C1206C104KRAC7800. Vitramon (R) chip capacitor: C11, C23: 2200 pF, VJ1206Y222KXA. Taconic(R) ORCER RF35: board material, 1 oz. copper, 30 mil thickness, r = 3.5.
Microstrip line: Z1 0.243 in. x 0.066 in.; Z2 0.050 in. x 0.066 in.; Z3 0.321 in. x 0.050 in.; Z4 0.047 in. x 0.066 in.; Z5 0.067 in. x 0.066 in.; Z6 0.123 in. x 0.066 in.; Z7 0.050 in. x 0.066 in.; Z8 0.381 in. x 0.066 in.; Z9 0.896 in. x 0.150 in.; Z10 0.050 in. x 0.600 in.; Z11 0.540 in. x 0.600 in.; Z12 0.050 in. x 0.600 in.; Z13 1.024 in. x 0.050 in.; Z14 0.093 in. x 0.500 in.; Z15 0.050 in. x 0.500 in.; Z16 0.242 in. x 0.500 in.; Z17 0.050 in. x 0.500 in.; Z18 0.198 in. x 0.500 in.; Z19 0.446 x 0.100; Z20 0.095 in. x 0.066 in.; Z21 0.050 in. x 0.066 in.; Z22 0.419 in. x 0.066 in.; Z23 0.745 in. x 0.066 in.; Z24 2.048 in. x 0.050 in. ATC(R) chip capacitor: C5: 4.7 pF 100B4R7BW; C4, C18 3.9 pF 100B3R9BW; C6, C7: 12 pF 100B120JW; C16, C17: 9.1 pF 100B9R1BW; C9, C21: 10 pF 100B100JW; C2: 47 pF 100A470JW; C3, C8, C19, C20: 47 pF 100B470JW; C1: 8.2 pF 100A8R2BW. 1206 size, 0.25 W, fixed film, chip resistors: R1 50 , RM73B2B500J; R2 47 k RM73B2B473J; R3 1 k RM73B2B103J; R4 10 RM73B2B100J.
B. Component Layout Figure 2. AGR18125E Test Circuit
AGR18125E 125 W, 1.805 GHz--1.880 GHz, LDMOS RF Power Transistor
Product Brief
Typical Performance Characteristics
0.0 > WA VELE N GTH S TOW A RD 0.0 0.49 0.48 180 170
U CT
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
3.0
4.0
5.0
10
20
LOA D <
0.49
OW A RD 7 HST 0.4 N GT -170 EL E AV W 0 < -90 -16
0.1
0.48
) / Yo (-jB CE
0.6
-85
AN PT CE US ES
1. 0
0.2
4 0.0 0 -15 -80
IV CT
0.4
DU
0.3
6
-75
,O o)
5
5 0.4
Z X/
-70
06
0.
-65
0.6
-60
1.6
0.7
1.4
0.8
1.2
5
0.9
-5
1.0
0
-5
5
-4
MHz (f) 865 (f1) 880 (f2) 895 (f3)
ZL ZS (Complex Source Impedance) (Complex Optimum Load Impedance) 0.980 - j2.93 2.54 + j0.868 0.865 - j2.90 2.58 + j0.819 0.710 - j2.81 2.60 + j0.765 GATE (2) ZS DRAIN (1) ZL SOURCE (3)
INPUT MATCH
DUT
OUTPUT MATCH
Figure 3. Series Equivalent Input and Output Impedances
F
0.
32
0.
1.8
18
0 -5 -25
4
4 0.
5
0.
0.3
0.1
3
2.
0
7
-30
-60
0.3
0.1
4
6
-
35
-70
0.35
0.15
0.36
0.14 -80
-4
0
0.37
0.13
0.4
0.2
-90
0.12
0.38
0.11 -100
0.39
CA P AC I TI
0.1
0.4
-110
VE
RE AC TA N
0.0
0.4
9
1
-12
CE CO M
0
0.0
PO N
0.4
8
2
EN
T
(-j
-1
0.
40
4
ZS
-20
0.0
3.
0
f1
0.6
f3
R
IN
-10
0.
8
10
f3
ZL
0.4
20
f1
0.2
50
RESISTANCE COMPONENT (R/Zo), OR CONDUCTANCE COMPONENT (G/Yo)
50
5.0
-15
4.0
1.
0
0.8
0.6
0.4
Z0 = 6
IN D
90
0.
8
10 0.1
-1
0.25 0.26 0.24 0.27 0.23 0.25 0.24 0.26 0.23 0.27 REFLECTION COEFFICIEN T IN DEG REES LE OF ANG ISSION COEFFI CIEN T IN TRA N SM D EGR EES
20
L E OF ANG
0.2
50
-20
0.2 2
0.2 8
0.2
1 -30
0.2 0.3
0.2 9
-4 0
0. 19 0. 31
0. 07 30 0.
43
Product Brief
AGR18125E 125 W, 1.805 GHz--1.880 GHz, LDMOS RF Power Transistor
Typical Performance Characteristics (continued)
Figure 4. Power Gain vs. POUT
Figure 5. Modulation Spectrum vs. POUT
Figure 6. Efficiency vs. POUT
Figure 7. Modulation Spectrum, Gain, and Efficiency vs. Frequency
Figure 8. Power Gain and Return Loss vs. Frequency
Figure 9. POUT and Efficiency vs. PIN
AGR18125E 125 W, 1.805 GHz--1.880 GHz, LDMOS RF Power Transistor
Product Brief
Package Dimensions
All dimensions are in inches. Tolerances are 0.005 in. unless specified.
AGR18125EU
PINS: 1. DRAIN 2. GATE 3. SOURCE
1
A M-AGR21125U YYWWUR ZZZZZZZ
PEAK DEVICES AGR18125XU YYWWLL XXXXX ZZZZZZZ
3
1
3 2
2
AGR18125EF
PINS: 1. DRAIN 2. GATE 3. SOURCE
1
1 3 3
M-AGR21125F YYWWUR ZZZZZZZ
2
PEAK DEVICES AGR18125XF YYWWLL XXXXX ZZZZZZZ
2
Label Notes: M before the part number denotes model program. X before the part number denotes engineering prototype. The last two letters of the part number denote wafer technology and package type. YYWWLL is the date code including place of manufacture: year year work week (YYWW), LL = location (AL = Allentown, PA; T = Thailand). XXXXX = five-digit wafer lot number. ZZZZZZZ = seven-digit assembly lot number on production parts. ZZZZZZZZZZZZ = 12-digit (five-digit lot, two-digit wafer, and five-digit serial number) on models and engineering prototypes.

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